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Slave Port Interface
Table 8-8. Slave Port I 2 C Address Register (SP_ADDR) field descriptions
Bit(s)
7
6-0
Field
—
ADDR
Reserved
See detailed description above.
Description
8.4.2.4
Slave Port Status and Control register
7
6
5
4
3
2
1
0
Read
ACTIVE
EN
PS
STOP_EN
RIE
WIE
WUP
Write
CSR
Reset
0
0
0
0
0
0
0
0
= Unimplemented or reserved
Figure 8-8. Slave Port Status and Control register (SP_SCR)
Table 8-9. Slave Port Status and Control register (SP_SCR) field descriptions
Bit(s)
7
6
5
Field
EN
PS
ACTIVE
Description
Slave Port Enable
Note: Note: On devices that support only the of SPI or I 2 C interface, this register bit is read-only.
Note: This bit it initialized to 1 by the boot manager at startup.
Note: EN should be switched high only when the slave port bus is known to be inactive.
0 Slave port is not enabled. Use this only for the instance where this device has no host controller.
1 Either SPI or I 2 C slave port is enabled (based on choice of PS bit).
Port Select
On devices that support only the of SPI or I 2 C interface, this register bit is read-only and fixed to the
appropriate value as per Table 8-8 .
On the MMA955xL, the PS bit is initialized by the boot manager at startup. If SSB (RGPIO3) is found to
be low during the boot process (immediately following any reset), the PS is set to 1 (SPI mode).
Otherwise, I 2 C mode is assumed.
The PS bit can be changed at later times as long as the slave port is disabled.
Note: Normally, both EN and PS are “set and forget” controls. Indiscriminately switching between
modes may result in loss of data unless extreme care is taken at the system level.
0 The I 2 C interface has been selected for use as slave port.
1 The SPI interface has been selected for use as slave port.
ACTIVE/CSR
Slave port is active
The function of this bit is dependent on the state of the PS bit.
This bit is not applicable with EN is 0.
CSR
Clear Read and Write Status Registers
This bit always reads as 0. Write a 1 to clear all four write status registers and all four read status
registers.
0 Clear Read and Write Status Registers
1 Clear SP_WSTS0, 1, 2 and 3 and SP_RSTS0, 1, 2 and 3.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
127
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